Description:System-on-Chip Resource Isolation
Author(s):Philippe Ledent, Radu Mateescu, Wendelin Serwe
Event(s): MARS'24
Paper(s): Testing Resource Isolation for System-on-Chip Architectures


Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.


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    3. tool(s): LNT (CADP)
    1. Download Model
    2. Browse Model
    3. tool(s): PSS
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